?¨?é??????DDR layout guide??Ethernet PHY layout guide.
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DDR in PC: Clock length match should be +/-10mil per pair impendance is 100ohm;
Data: +/-50mil, 60ohm;
Addr/Control: +/-1inch, 50ohm;
...
So you also need control the trace's width,space and PCB stackup
LAN: TX+ and TX- should be +/-100mil in 100M. and +/-30mil(at least 50mil) in 1000M.